A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS

Hao Li; Chun-Ming Hsu; Jahnavi SharmaJames JaussiGanesh Balamurugan

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A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS

机译：A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS

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摘要

Optical receivers (ORXs) with integrated CMOS electronics enable compact, low-power solutions for 400-G Ethernet and co-packaged optics. In this article, we present a 100-Gb/s PAM-4 ORX with TIA and sampler integrated into a single 28-nm CMOS IC. ORX sensitivity is optimized using a low noise, sub-Nyquist bandwidth TIA followed by a mixed signal sampler that includes 2-tap FFE and 2-tap DFE. A distributed current-integrating summer helps meet feedback latency requirements of 50-Gbaud direct-feedback PAM-4 DFE. Measurements characterizing the CMOS linear TIA indicate ~23-GHz trans-impedance (ZT) bandwidth (BW) with- $2.5~mu text{A}_{mathrm {rms}}$ input-referred noise. Optical measurement results at 100 Gb/s show that ?8.9-dBm sensitivity is achieved at 2.4e-4 BER with 3.9-pJ/bit energy efficiency.

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来源
《IEEE Journal of Solid-State Circuits》 |2022年第1期|44-53|共10页
作者
Hao Li; Chun-Ming Hsu; Jahnavi SharmaJames JaussiGanesh Balamurugan;
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作者单位

Intel Corporation, Hillsboro, OR, USA;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
Decision feedback equalizers; Sensitivity; Integrated circuits; Optical signal processing; Optical receivers; Semiconductor device modeling; Latches;

A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS

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