Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

Rosenblatt S.; Fainstein D.; Cestero A.Safran J.Robson N.Kirihata T.Iyer S.S.

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Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

机译：Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

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摘要

A random intrinsic chip ID generation method using retention fails is implemented in 32 nm SOI embedded DRAM. A dynamic key algorithm employs a unique pair of 4 Kb binary strings for an ID record for secure authentication. These strings are generated by controlling a wordline low voltage to search for a number of fails matching the corresponding challenge numbers. The algorithm further includes field-tolerant authentication by detecting a number of common bits analytically guaranteed for successful recognition, while preventing ID spoofing during the read operation. This results in 100% successful unique ID generation and recognition in two temperature and three voltage conditions per chip for a total of $sim$ 420 k ID pair comparisons in 266 chips. The analytical model predicts a 99.999% successful recognition rate for 10 $^{6}$ parts. Finally, a method to enable a field-tolerant ID using multiple domains will be discussed.

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来源
《IEEE Journal of Solid-State Circuits》 |2013年第4期|940-947|共8页
作者
Rosenblatt S.; Fainstein D.; Cestero A.Safran J.Robson N.Kirihata T.Iyer S.S.;
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作者单位

IBM Systems and Technology Group, NY, USA;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
Arrays; Authentication; Hardware; Heuristic algorithms; IP networks; Random access memory; Embedded DRAM; hardware counterfeit; hardware security; intrinsic ID; physically unclonable functions;

Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

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