A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

Howard J.; Dighe S.; Vangal S. R.Ruhl G.Borkar N.Jain S.Erraguntla V.Konow M.Riepen M.Gries M.Droege G.Lund-Larsen T.Steibl S.Borkar S.De V. K.Van Der Wijngaart R.

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A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

机译：A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

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This paper describes a multi-core processor that integrates 48 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 6$,times,$4 2D-mesh network-on-chip architecture. Located at each mesh node is a five-port virtual cut-through packet-switched router shared between two IA-32 cores. Core-to-core communication uses message passing while exploiting 384 KB of on-die shared memory. Fine grain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. At the nominal 1.1 V supply, the cores operate at 1 GHz while the 2D-mesh operates at 2 GHz. As performance and voltage scales, the processor dissipates between 25 W and 125 W. The $567~{hbox {mm}}^{2}$ processor is implemented in 45 nm Hi-K CMOS and has 1.3 billion transistors.

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《IEEE Journal of Solid-State Circuits》 |2011年第1期|173-183|共11页
作者
Howard J.; Dighe S.; Vangal S. R.Ruhl G.Borkar N.Jain S.Erraguntla V.Konow M.Riepen M.Gries M.Droege G.Lund-Larsen T.Steibl S.Borkar S.De V. K.Van Der Wijngaart R.;
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作者单位

Intel Corporation, Hillsboro, OR, USA;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
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关键词
2D-routing; CMOS digital integrated circuits; DDR3 controllers; IA-32; dynamic voltage frequency scaling (DVFS); message passing; network-on-chip (NoC);

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

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