This paper presents a technique to reduce the quantization error in fractional division for a wideband fractional- $N$ frequency synthesizer. By using a direct digital synthesis phase accumulator as the fractional divider and a DAC as the phase-to-pulse converter, the quantization error can be much smaller than the one by conventional sigma-delta modulated multi-modulus divider. With small quantization error, a dedicated compensation mechanism is no longer necessary for wide loop bandwidth applications. To demonstrate this concept, a prototype chip was implemented with 0.18- $mu{hbox {m}}$ CMOS. The synthesizer consumes 19 mA from a 1.8 V supply. With 1 MHz closed-loop bandwidth, the in-band noise is ${- }{hbox {98~dBc}}/{hbox {Hz}}$ and the 3 MHz offset noise is ${- }{hbox {122~dBc}}/{hbox {Hz}}$ for a 1.8 GHz output. The output exhibited 27 dB phase noise reduction compared to the generic sigma-delta structure. The settling time is 2 $mu{hbox {s}}$ under a 35 MHz frequency step.
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