Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback

Sukumaran A.; Pavan S.

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Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback

机译：Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback

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摘要

Single-bit continuous-time delta-sigma modulators (CTDSM) using FIR feedback DACs inherit the appealing aspects of both single-bit and multibit designs, without the disadvantage of either approaches. In this work, we give a method for stabilizing a CTDSM that uses an FIR feedback DAC. Further, we show that increasing the number of taps beyond a certain number (dependent on the architecture and oversampling ratio of the modulator) does not improve performance. The results of our analysis are incorporated in the design of a third-order audio CTDSM which achieves a peak A-weighted SNR of 102.3 dB (raw SNR of 98.9 dB) and a spurious-free dynamic range of 106 dB in a 24 kHz bandwidth, while consuming only 280 μW from a 1.8 V supply.

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《IEEE Journal of Solid-State Circuits》 |2014年第11期|2515-2525|共11页
作者
Sukumaran A.; Pavan S.;
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作者单位

CSD 203, VLSI Lab, Electrical Engineering Dept., Indian Institute of Technology Madras, Chennai, India;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
Clocks; Finite impulse response filters; Frequency modulation; Jitter; Noise; Quantization (signal); Active-RC; FIR DAC; Sigma-Delta; analog-to-digital conversion; compensation; continuous-time; integrator; oversampling;

Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback

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