A 25-Gb/s 5-mW CMOS CDR/Deserializer

Jung J. W.; Razavi B.

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A 25-Gb/s 5-mW CMOS CDR/Deserializer

机译：A 25-Gb/s 5-mW CMOS CDR/Deserializer

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摘要

The demand for higher data rates in serial links has exacerbated the problem of power consumption, motivating extensive work on receiver and transmitter building blocks. This paper presents a half-rate clock and data recovery circuit and a deserializer that employ charge-steering logic to reduce the power consumption. Realized in 65-nm technology, the overall circuit draws 5 mW from a 1-V supply, producing a clock with an rms jitter of 1.5 ps and a jitter tolerance of 0.5 UI$_{rm pp}$ at 5 MHz jitter frequency.

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来源
《IEEE Journal of Solid-State Circuits》 |2013年第3期|684-697|共14页
作者
Jung J. W.; Razavi B.;
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作者单位

Electrical Engineering Department, University of California, Los Angeles,;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
Clocks; Detectors; Jitter; Latches; Optical signal processing; Topology; Transistors; Charge steering; clock and data recovery; deserializer; phase detecter;

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A 25-Gb/s 5-mW CMOS CDR/Deserializer

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