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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3amp;italicamp;σamp;/italicamp; Inaccuracy of +0.02, ?0.12 for Battery-Monitoring Applications
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A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3amp;italicamp;σamp;/italicamp; Inaccuracy of +0.02, ?0.12 for Battery-Monitoring Applications

机译：A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3amp;italicamp;σamp;/italicamp; Inaccuracy of +0.02, ?0.12 for Battery-Monitoring Applications

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This article presents a single-trim switched capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. For a single-temperature trimming, &inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"& &tex-math notation="LaTeX"&$beta $ &/tex-math&&/inline-formula&-compensation and curvature correction techniques are employed to minimize non-proportional-to-absolute-temperature (PTAT) errors. In conjunction with these techniques, this article proposes dynamic element matching (DEM) techniques with low-pass filtering which employs the decimation filter of a delta-sigma analog-to-digital converter (ADC) in a digital domain. It achieves a further reduction of non-PTAT errors resulting from mismatches of the bias current, of the PNP transistor current gain (&inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"& &tex-math notation="LaTeX"&$beta $ &/tex-math&&/inline-formula&), and of the gain coefficient in the SC summing amplifier. The remaining PTAT errors are canceled out using a single room-temperature trimming. The bandgap circuit is implemented using vertical PNP transistors with a &inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"& &tex-math notation="LaTeX"&$beta $ &/tex-math&&/inline-formula& of about 2.7 at 27 °C in a 0.18-&inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"& &tex-math notation="LaTeX"&$mu text{m}$ &/tex-math&&/inline-formula& CMOS process. The proposed SC BGR achieves a &inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"& &tex-math notation="LaTeX"&$3sigma $ &/tex-math&&/inline-formula& inaccuracy of +0.02%, ?0.12% from ?40 °C to 125 °C. From a 1.8-V supply voltage, it consumes &inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"& &tex-math notation="LaTeX"&$17~mu text{A}$ &/tex-math&&/inline-formula& at 27 °C and occupies an active area of 0.38 mm&sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"&2&/sup&.

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