This paper presents an energy-efficient successive approximation register (SAR)-assisted digital-slope analog-to-digital converter (ADC) architecture for high-resolution applications. The proposed hybrid ADC combines a low-noise fine digital-slope ADC with a low-power coarse SAR ADC. The coarse SAR ADC rapidly approximates the input signal and produces a small residue signal for the succeeding fine ADC. The fine digital-slope ADC linearly approaches the small residue signal. A prototype was fabricated in 1P8M 28 nm CMOS technology. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio of 64.43 dB and a spurious free dynamic range of 75.42 dB at the Nyquist input frequency while consuming 0.35 mW from a 0.9 V supply. The resultant Walden and Schreier figures of merit are 2.6 fJ/conversion-step and 176.0 dB, respectively. The ADC occupies an active area of 66μm×71μm .
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