A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS

Sundstrom T.; Svensson C.; Alvandpour A.

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A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS

机译：A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS

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摘要

This paper presents a high-speed single-channel pipeline analog-to-digital converter sampling at 2.4 GS/s. The high sample rate is achieved through the use of fast open-loop current-mode amplifiers and the early comparison scheme. The bounds on the sub-ADC sampling instance are analyzed based on sufficient settling for a decision as well as metastability. Implemented in a 65 nm general purpose CMOS technology the SNDR is above 30.1 dB in the Nyquist band, being 34.1 and 31.3 dB at low frequency and Nyquist, respectively. This shows that multi-GS/s pipeline ADCs are feasible as key building blocks in interleaved structures.

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来源
《IEEE Journal of Solid-State Circuits》 |2011年第7期|1575-1584|共10页
作者
Sundstrom T.; Svensson C.; Alvandpour A.;
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作者单位

Department of Electrical Engineering, Linkö

ping University, Linkö

ping, Sweden;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
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关键词
Analog-to-digital converter (ADC); CMOS analog integrated circuits; current-mode; data converter; foreground digital calibration; high speed; low power; pipeline;

A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS

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