A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization

Taejoong Song; Woojin Rim; Sunghyun ParkYongho KimGiyong YangHoonki KimSanghoon BaekJonghoon JungBongjae KwonSungwee ChoHyuntaek JungYongjae ChooJaeseung Choi

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A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization

机译：A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization

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摘要

Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology. A 0.040 μm2 6T SRAM bitcell is designed for high density (HD), and 0.049 μm2 for high performance (HP). The various SRAM assist schemes are explored to evaluate the power, performance, and area (PPA) gain, and the figure-of-merit (FOM) is induced by the minimum operating voltage (VMIN) and assist overheads. The dual-transient wordline scheme is proposed to improve the VMIN by 47.5 mV for the 128 Mb 6T-HP SRAM. The suppressed bitline scheme with negative bitline improves the VMIN by 135 mV for the 128 Mb 6T-HD SRAM. The FOM of PPA gain evaluates the optimum SRAM assist for the different bitcells based on the applications.

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来源
《IEEE Journal of Solid-State Circuits》 |2017年第1期|240-249|共10页
作者
Taejoong Song; Woojin Rim; Sunghyun ParkYongho KimGiyong YangHoonki KimSanghoon BaekJonghoon JungBongjae KwonSungwee ChoHyuntaek JungYongjae ChooJaeseung Choi;
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作者单位

Samsung Electronics Company, Ltd., Hwaseong, South Korea;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
Random access memory; Resistance; FinFETs; Timing; High definition video; Metals; Market research;

A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization

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