A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter

Tokairin T.Okada M.Kitsunezuka M.Maeda T.Fukaishi M.

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A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter

机译：A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter

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摘要

A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The time-windowed TDC uses a two-step structure with an inverter- and a Vernier-delay time-quantizer to improve time resolution, which results in low phase noise. Time-windowed operation is implemented in the TDC, in which a single-shot pulse-based operation is used for low power consumption. The test chip implemented in 90-nm CMOS technology exhibits in-band phase noise of $-{hbox {105~dBc}}/{hbox {Hz}}$, where the loop-bandwidth is set to 500 kHz with a 40-MHz reference signal, and out-band noise of $-{hbox {115~dBc}}/{hbox {Hz}}$ at a 1-MHz offset frequency. The chip core occupies 0.37 ${hbox {mm}}^{2}$ and the measured power consumption is 8.1 mA from a 1.2-V power supply.

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来源
《IEEE Journal of Solid-State Circuits》 |2010年第12期|2582-2590|共9页
作者
Tokairin T.Okada M.Kitsunezuka M.Maeda T.Fukaishi M.;
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作者单位

Device Platforms Research Laboratories, NEC Corporation, Kawasaki, Japan;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
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关键词
$Delta Sigma $ modulator; all-digital phase locked loop (ADPLL); digitally controlled oscillator (DCO); frequency synthesizer; higher-order modulation; phase noise; quantization noise; synchronous counter; time-to-digital converter (TDC);

A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter

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