ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET

Haidang Lin; Charlie Boecker; Masum HossainShankar TangiralaRoxanne VuSocrates D. VamvakosEric GroenSimon LiPrashant ChoudharyNanyan WangMasumi ShibataHossein TaghaviMarcus van IersselAdilHussain ManiyarAdam WodkowskiKulwant BrarNhat NguyenShaishav Desai

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ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET

机译：ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET

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This article describes a 4 &inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"& &tex-math notation="LaTeX"&$times $ &/tex-math&&/inline-formula& 112 Gb/s digital receiver targeting long-reach (LR) channels. An SNR optimized approach is presented, which relaxes the ADC resolution requirement and the number of FFE taps without sacrificing BER. The discrete-time front end overcomes gain–BW limitations to provide 10+ dB gain at 28 GHz. A 56-GS/s ADC then converts the signal to 6-b digital consuming only 195 mW. The following DFE-FFE-based digital equalizer is capable of compensating 36-dB loss achieving a BER of 2e?5. Furthermore, TDC and ISI filter-based low-latency timing recovery meet jitter tolerance specs over a wide range of data rates from 10 to 112 Gb/s, including 28-Gb/s NRZ. The overall receiver consumes 338 mW with 3.18-pJ/bit energy efficiency.

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来源
《IEEE Journal of Solid-State Circuits》 |2021年第4期|1265-1277|共13页
作者
Haidang Lin; Charlie Boecker; Masum HossainShankar TangiralaRoxanne VuSocrates D. VamvakosEric GroenSimon LiPrashant ChoudharyNanyan WangMasumi ShibataHossein TaghaviMarcus van IersselAdilHussain ManiyarAdam WodkowskiKulwant BrarNhat NguyenShaishav Desai;
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作者单位

Rambus Inc., San Jose, CA, USA;

University of Alberta, Edmonton, Canada;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
Receivers; Decision feedback equalizers; Signal to noise ratio; Timing; Gain; Frequency response; Power demand;

ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET

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