Reconfigurable architecture of RNS based high speed FIR filter

J Britto Pari; S P Joy Vasantha Rani

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Reconfigurable architecture of RNS based high speed FIR filter

机译：Reconfigurable architecture of RNS based high speed FIR filter

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摘要

In this paper, a high speed reconfigurable FIR filter with multiple taps using accumulator based radix-4 multiplier is proposed. The 3n-bit binary input is converted into three residues using binary to residue number system (RNS) converter and then processed in three FIR sub filters constructed in direct form. The filter structure is implemented with a multiply and accumulate (MAC) architecture using accumulator based radix-4 multiplier. The reconfigurable structure is achieved by combining power of two (PoT) FIR sub modules and the coefficients are altered during runtime. The proposed design is tested and implemented for 20-tap FIR filter. The architecture is implemented using VHDL and synthesized using Altera cyclone II EP2C35F672C6. The performance results show that the architecture achieves low power and high speed and variable tap flexibility.

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来源
《Indian journal of engineering and materials sciences》 |2014年第2期|233-240|共8页
作者
J Britto Pari; S P Joy Vasantha Rani;
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作者单位

Department of Electronics Engineering, MIT Campus, Anna University, Chennai 600 025, India;

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原文格式 PDF
正文语种英语
中图分类工程材料学;
关键词
FIR filter; Residue number system; Higher radix multiplier; Reconfigurable architecture; Power of two;

Reconfigurable architecture of RNS based high speed FIR filter

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