A 2.3 GHz 2.8 mW Sampling ΔΣ PLL Achieving ?110 dBc/Hz In-Band Phase Noise and 500 MHz FMCW Chirp

Hanyang Su; Jingcheng Tao; Siegfred D. BalonChun-Huat Heng

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A 2.3 GHz 2.8 mW Sampling ΔΣ PLL Achieving ?110 dBc/Hz In-Band Phase Noise and 500 MHz FMCW Chirp

机译：A 2.3 GHz 2.8 mW Sampling ΔΣ PLL Achieving ?110 dBc/Hz In-Band Phase Noise and 500 MHz FMCW Chirp

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摘要

A phase interpolator (PI)-free fractional-inline-formula tex-math notation="LaTeX"$N$ /tex-math/inline-formula sampling phase-locked loop (SPLL) has been proposed and implemented in 130 nm CMOS technology, which eliminates time-domain PI, digital-to-time converter (DTC), or background calibration. This phase-locked loop (PLL) employs two linear slope generators (LSGs) to produce linear waveforms, which are related to the VCO feedback phase. Then the reference directly samples the LSG outputs to obtain the phase error. Following this, a 3 bit DAC-based phase interpolating charge pump (PICP) is utilized to interpolate the phase error before feeding it to the loop filter. This enables the SPLL to achieve a fractional-inline-formula tex-math notation="LaTeX"$N$ /tex-math/inline-formula ratio without any DTC or calibration. On-chip frequency-modulated continuous-wave (FMCW) chirp generation is also included, which provides 500 MHz FMCW chirp with reconfigurable chirp rate and up to 25% chirp bandwidth to carrier frequency ratio. It consumes 2.8 mW from a 1.2 V supply and occupies an active area of about 0.4 mmsup2/sup. With a 50 MHz crystal reference, the in-band phase noise is measured to be 109 dBc/Hz at 200 kHz offset. The FoM for the system is measured as ?243~ ?247.5 dB.

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来源
《IEEE Journal of Solid-State Circuits》 |2021年第11期|3458-3469|共12页
作者
Hanyang Su; Jingcheng Tao; Siegfred D. BalonChun-Huat Heng;
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作者单位

Electrical and Computer Engineering Department, National University of Singapore, Singapore;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
Voltage-controlled oscillators; Phase locked loops; Phase noise; Interpolation; Chirp; Time-domain analysis; Linearity; Calibration-free; CMOS; digital-to-time converter (DTC)-free; fractional-italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/199; frequency-modulated continuous-wave (FMCW); low phase noise; low power; phase interpolator (PI)-free; phase-locked loop (PLL); subsampling PLL (SSPLL);

A 2.3 GHz 2.8 mW Sampling ΔΣ PLL Achieving ?110 dBc/Hz In-Band Phase Noise and 500 MHz FMCW Chirp

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