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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 1 V Input, 3 V-to-6 V Output, 58-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics
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A 1 V Input, 3 V-to-6 V Output, 58-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics

机译：A 1 V Input, 3 V-to-6 V Output, 58-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics

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摘要

This paper presents an integrated hybrid 6-stage voltage multiplier without using high-voltage-tolerant devices. The proposed architecture obtains a good area and efficiency performance by cascading the Dickson charge pumps and the symmetrical Cockcroft-Walton charge pumps, and paralleling them with the proposed auxiliary charge pumps formed by parasitics. Implemented in a standard 0.18 mu m CMOS process, the prototype provides a wide output range of 3-6 V and 30-240 mu A load from a 1 V supply with an efficiency of 48-58% (52% at the 6 V output when the gain is six). By using on-chip MOS capacitors as the flying capacitors, an area reduction of 66% as compared to the Dickson charge-pump of similar performance is achieved. The area shrinks to 0.05 mm(2) per 9x interleaved cell. The entailed efficiency loss due to parasitics is compensated by the proposed auxiliary parasitic pumping paths feeding forward to redirect the parasitic charge flow. With this technique, the efficiency enhances extra 11%. The technique is applicable to other on-chip charge-pumps.

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