Study of self-aligned doped channel MOSFET structure for low power and low 1/f noise operation

Yoshitomi  Takashi; Ishizuka  Shinnichiro; Miyahara  YasunoriOhguro  TatsuyaMorifuji  EijiMorimoto  ToyotaMomose  Hisayo SasakiKatsumata  YasuhiroIwai  HiroshiKimijima  Hideki

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Study of self-aligned doped channel MOSFET structure for low power and low 1/f noise operation

机译：Study of self-aligned doped channel MOSFET structure for low power and low 1/f noise operation

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摘要

A self-Aligned Doped Channel (SADC) is proposed and investigated for the first time. In the SADC process, the channel doping process is carried out by using solid phase diffusion from the gate; hence the doping region is fully self-aligned to the gate, and the junction capacitance can be reduced. In addition, the implantation damage in the channel is reduced. We obtained 0.25 µm gate length nMOSFETs with low noise and low power consumption by using the SADC structure. Hence, this structure is attractive for small geometry RF CMOS devices.

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来源
《Solid-State Electronics》 |1999年第7期|1219-1224|共6页
作者
Yoshitomi Takashi; Ishizuka Shinnichiro; Miyahara YasunoriOhguro TatsuyaMorifuji EijiMorimoto ToyotaMomose Hisayo SasakiKatsumata YasuhiroIwai HiroshiKimijima Hideki;
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作者单位

Toshiba Corp;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
原文格式 PDF
正文语种英语
中图分类一般性问题;
关键词
Semiconductor device structures; MOSFET devices; Gates (transistor); Semiconductor doping; Diffusion; Capacitance; CMOS integrated circuits; Self aligned doped channel; Channel doping; Solid phase diffusion; Implantation damage; Gate length;

Study of self-aligned doped channel MOSFET structure for low power and low 1/f noise operation

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