A 31 ns Random Cycle VCAT-Based 4Fformula formulatype='inline'  img src='/images/tex/732.gif' alt='^{2}' /formula DRAM With Manufacturability and Enhanced Cell Efficiency

Song K.-W.

首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 31 ns Random Cycle VCAT-Based 4Fformula formulatype='inline' img src='/images/tex/732.gif' alt='^{2}' /formula DRAM With Manufacturability and Enhanced Cell Efficiency

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A 31 ns Random Cycle VCAT-Based 4Fformula formulatype='inline' img src='/images/tex/732.gif' alt='^{2}' /formula DRAM With Manufacturability and Enhanced Cell Efficiency

机译：A 31 ns Random Cycle VCAT-Based 4Fformula formulatype="inline" img src="/images/tex/732.gif" alt="^{2}" /formula DRAM With Manufacturability and Enhanced Cell Efficiency

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摘要

A functional ${hbox{4F}}^{2}$ DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance VCAT has been developed showing excellent Ion-Ioff characteristics with more than twice turn-on current compared with the conventional recessed channel access transistor (RCAT). A new design methodology has been applied to accommodate ${hbox{4F}}^{2}$ cell array, achieving both high performance and manufacturability. Especially, core block restructuring, word line (WL) strapping and hybrid bit line (BL) sense-amplifier (SA) scheme play an important role for enhancing AC performance and cell efficiency. A 50 Mb test chip was fabricated by 80 nm design rule and the measured random cycle time (tRC) and read latency (tRCD) are 31 ns and 8 ns, respectively. The median retention time for 88 Kb sample array is about 30 s at 90$,^{circ}$ C under dynamic operations. The core array size is reduced by 29% compared with conventional ${hbox{6F}}^{2}$ DRAM.

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来源
《IEEE Journal of Solid-State Circuits》 |2010年第4期|共9页
作者
Song K.-W.;
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作者单位

DRAM Development Group, Memory Division, Samsung Electronics Co., Hwasung-City, Korea;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类 NULL;
关键词
4F $^{2}$; DRAM; cell efficiency; core architecture; hybrid sense-amplifier (SA); stack capacitor; surrounding-gate vertical channel access transistor (VCAT);

A 31 ns Random Cycle VCAT-Based 4Fformula formulatype='inline' img src='/images/tex/732.gif' alt='^{2}' /formula DRAM With Manufacturability and Enhanced Cell Efficiency

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