With the further shrinking of IC dimensions, low-${~hbox {k}}$ material has been widely used to replace the traditional SiO$_{2}$ interlayer dielectric (ILD) in order to reduce the interconnect delay. The introduction of low-${hbox {k}}$ material into silicon imposed challenges on dicing saw process. ILD and metal layers peeling and its penetration into the sealing ring of the die during dicing saw are the most common defects. In this paper, the low-${hbox {k}}$ material structure and its impact on wafer dicing were elaborated. A practical dicing quality inspection matrix was developed to assess the cutting process variation. A 300-mm CMOS90-nm dual damascene low-${hbox {k}}$ wafer was chosen as a test vehicle to develop a robust low-${hbox {k}}$ dicing saw process. The critical factors (dicing blade, index speed, spindle speed, cut in depth, test pattern in the saw street, etc.) affecting cutting quality were studied and optimized. The selected C90 Dual damascene low- ${hbox {k}}$ device passed package reliability tests with the optimized low-${hbox {k}}$ dicing saw recipe and process. The further improvement and solutions in eliminating the low-${hbox {k}}$ dicing saw peeling were also explored.
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