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机译:A 16 MHz BW 75 dB DR CT $DeltaSigma$ ADC Compensated for More Than One Cycle Excess Loop Delay
Texas Instruments (India) Pvt. Ltd., Bangalore, India;
Analog-to-digital converter (ADC); compensation; continuous-time; delta-sigma; excess loop delay (ELD); oversampling; quantizer; sample and hold (S/H);