A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 x 16 Network-on-Chip in 22 nm Tri-Gate CMOS

Chen Gregory; Anders Mark A.; Kaul HimanshuSatpathy Sudhir K.Mathew Sanu K.Hsu Steven K.Agarwal AmitKrishnamurthy Ram K.De VivekBorkar Shekhar

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A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 x 16 Network-on-Chip in 22 nm Tri-Gate CMOS

机译：A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 x 16 Network-on-Chip in 22 nm Tri-Gate CMOS

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摘要

A 16 x 16 mesh network-on-chip (NoC) is fabricated in 22 nm tri-gate CMOS for high-throughput, energy-efficient on-chip interconnect in multi-core processors and systems-on-chip. The NoC connects 256 nodes that are each in their own voltage and clock domain using 5-port routers and 112 b, 855 mu m data links. Source-synchronous operation eliminates global clock distribution power and adapts to process, voltage, and temperature variations. Hybrid packet/circuit switching improves energy efficiency by removing intra-route data storage and increases throughput with parallel packet-switched channel setup and circuit-switched data transfer. The NoC achieves: i) 20.2 Tb/s total throughput at 0.9 V, 25 degrees C; ii) source-synchronous operation for a 2.7x increase in bisection bandwidth to 2.8 Tb/s and 93% reduction in circuit-switched latency at 407 ps/hop, compared to synchronous design; iii) hybrid packet/circuit switching for a 62% latency improvement and 55% increase in energy efficiency to 7.0 Tb/s/W, compared to packet switching; iv) a peak energy efficiency of 18.3 Tb/s/W for near-threshold operation at 430 mV, 25 degrees C; v) ultra-low-voltage operation down to 340 mV, 25 degrees C, with router power scaling to 363 mu W.

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来源
《IEEE Journal of Solid-State Circuits》 |2015年第1期|59-67|共9页
作者
Chen Gregory; Anders Mark A.; Kaul HimanshuSatpathy Sudhir K.Mathew Sanu K.Hsu Steven K.Agarwal AmitKrishnamurthy Ram K.De VivekBorkar Shekhar;
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作者单位

Intel Corp, Circuit Res Lab, Hillsboro, OR 97124 USA;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
Circuit switching; multiprocessor interconnect; near-threshold voltage circuits; network-on-chip (NoC); source-synchronous communication; ultra-low-voltage circuits;

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 x 16 Network-on-Chip in 22 nm Tri-Gate CMOS

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