In this article, we apply a new clock-phase reuse technique to a discrete-time infinite impulse response (IIR) complex-signaling bandpass filter (BPF). This leads to a deep improvement in filtering, especially the stopband rejection, while maintaining the area, sampling frequency, and the number of clock phases and their pulsewidths. Fabricated in 28-nm CMOS, the proposed BPF is highly tuneable and is capable of achieving a 70-dB stopband rejection at 50-MHz offset with 25% duty-cycle clocks while consuming 1.65 mW. The achieved in/out-of-band third-order intermodulation intercept point (IIP3) is +2.5 dB and +17.3 dBm, respectively, and the input-referred noise (IRN) is 1 ${mathrm {nV}}/{sqrt {mathrm{ Hz}}}$ .
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