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机译:A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging
Intel Corp, Circuit Res Lab, Hillsboro, OR 97124 USA;
Adaptation; domino read operation; error compaction; error detection sequentials; register file; resiliency; timing error detection; timing margin detection; tunable replica circuits;