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首页> 外文期刊>Signal Processing: The Official Publication of the European Association for Signal Processing (EURASIP) >VLSI generalized digit serial architecture for multiplication, division and square root
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VLSI generalized digit serial architecture for multiplication, division and square root

机译：VLSI generalized digit serial architecture for multiplication, division and square root

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摘要

A novel digit serial combined arithmetic unit for multiplication, division and square root which can be pipelined to the bit level is presented for the first time. The proposed module is based on radix-2 super(n) arithmetic. As a result, it is general for any digit size, n, and can be derived in a straightforward manner without the need to bit parallel or bit serial designs as an initial starting point. Moreover, any adder can be used in the controlled add/shift /subtract basic cell of the generalized digit serial unit. Two digital basic cells are proposed; the first cell is based on the conventional carry feedback adder and hence, the digit serial structure can be pipelined to the digit level only. The second digital cell is based on the carry fed forward adder. The feed forward of the carry out bit allows subdigit pipelining to increase the computation speed. This will give designers greater flexibility in finding the best trade-off between hardware cost and throughput rate. An evaluation of the proposed structure is also presented. It is shown that the bit level pipelined digit serial architecture can achieve better performance than the conventional carry feedback digit serial design and the bit parallel one.

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