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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Key Aspects in Modeling of Thin Epi SOS Technology With Application of BSIMSOI
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Key Aspects in Modeling of Thin Epi SOS Technology With Application of BSIMSOI

机译:Key Aspects in Modeling of Thin Epi SOS Technology With Application of BSIMSOI

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摘要

This work addresses the device modeling challenges of production-quality, state-of-the-art, silicon-on-sapphire (SOS) processes. Differences between SOS, silicon-on-insulator (SOI), and bulk CMOS are highlighted, with emphasis on the key differences in the modeling methodology. For RF and low-power applications, SOS has distinct advantages over SOI, such as reduced parasitics, better linearity, and enhanced electrical isolation. Yet little is reported in the literature about modeling of a commercially viable SOS process.

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