Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold

Ritter P.; Le Tual S.; Allard B.Moller M.

首页> 外文期刊>IEEE Journal of Solid-State Circuits >Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold

【24h】

Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold

机译：Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相关主题

摘要

A novel comparator placing scheme and reference ladder concept are presented for flash analog-to-digital converters (ADC), that minimize the dynamic reference voltage distortions at high signal speed. No track-and-hold or time interleaving is used in the ADC, which reduces the design complexity and minimizes the conversion latency. The data input signal is buffered by an emitter follower (EF) and distributed by a passive transmission line (TML) tree to the comparators. The EF and comparators are systematically optimized with respect to the energy efficiency and design considerations for the trade off between dynamic linearity and power dissipation are given in detail. The TML tree is designed such that in spite of inhomogeneous loading by the comparators equal transfer functions are achieved along all paths. The ADC achieves without calibration or correction an effective resolution beyond 3.7 bits up to 10 GHz signal frequency and 20 GS/s sampling. With 1.0 W of power dissipation the conversion efficiency is 3.9 pJ per conversion step, which sets a record for single-core ADCs beyond 10 GS/s Nyquist rate.

著录项

来源
《IEEE Journal of Solid-State Circuits》 |2014年第9期|1886-1894|共9页
作者
Ritter P.; Le Tual S.; Allard B.Moller M.;
展开▼
作者单位

Chair of Electronics and Circuits, Saarland University, Germany;

展开▼
收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
Capacitance; Clocks; Latches; Linearity; Quantization (signal); Resistors; Silicon germanium; Analog-to-digital converter; SiGe BiCMOS; comparator clipping; complementary A/D slice; emitter follower linearity; passive transmission line tree;

Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold

摘要

著录项

相关主题

期刊订阅