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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface
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A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface

机译：A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface

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摘要

A single-ended four-level pulse-amplitude modulation (PAM-4) transmitter (TX) for memory interfaces achieves high signal integrity by combining an impedance-matched PAM-4 driver with a three-point ZQ calibration scheme. This improves PAM-4 linearity by allowing the driver to compensate for its impedance variation caused by the change in the drain–source voltage (&inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"& &tex-math notation="LaTeX"&$V_{mathrm {DS}}$ &/tex-math&&/inline-formula&) to suit the four output levels considering both the TX and the receiver (RX). Resistors and inductors are eliminated from the voltage-mode (VM) driver, reducing the area requirement. The two-tap asymmetric feed-forward equalization (FFE) allocates six different coefficients to each minimum pull-up and pull-down transition, compensating for nonlinear equalization strengths and asymmetric characteristics of the driver. A prototype chip fabricated in the 65-nm CMOS has an area of 0.0333 mm&sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"&2&/sup& and consumes 0.64 pJ/bit. It achieves a data rate of 28 Gb/s/pin with a ratio level separation mismatch (RLM) of 0.993.

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