A 7-tap 40 Gb/s FFE using a 65 nm standard CMOS process is described. A number of broadbanding and calibration techniques are used, which allow high-speed operation while consuming 80 mW from a 1 V supply. ESD protection is added to 40 Gb/s IOs and an inexpensive plastic package is used to make the chip closer to a commercial product. The measured tap delay frequency response variation is less than 1 dB up to 20 GHz and tap-to-tap delay variation is less than 0.3 ps. More than 50% vertical and 70% horizontal eye opening from a closed input eye are observed. The use of a CMOS process enables further integration of this core into a DFE equalizer or a CDR/Demux based receiver.
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