DIGITAL FREQUENCY-LOCKED LOOP WITH WIDE LOCK-IN RANGE AND LOW FREQUENCY ERROR BASED ON MULTI-PHASE CLOCK

MITSUTOSHI YAHARA; KUNIAKI FUJIMOTO; DAISHI NISHIGUCHIYUJIRO HARADAMASAAKI FUKUHARA

首页> 外文期刊>International journal of innovative computing, information and control >DIGITAL FREQUENCY-LOCKED LOOP WITH WIDE LOCK-IN RANGE AND LOW FREQUENCY ERROR BASED ON MULTI-PHASE CLOCK

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DIGITAL FREQUENCY-LOCKED LOOP WITH WIDE LOCK-IN RANGE AND LOW FREQUENCY ERROR BASED ON MULTI-PHASE CLOCK

机译：DIGITAL FREQUENCY-LOCKED LOOP WITH WIDE LOCK-IN RANGE AND LOW FREQUENCY ERROR BASED ON MULTI-PHASE CLOCK

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An all-digital frequency-locked loop (DFLL) using a multi-phase clock-based 1 + 1/k divider has been proposed. This circuit can reduce the jitter of the output signal extremely small. However, it has the problem of a narrow lock-in range. In this paper, we propose a DFLL with a wide frequency lock-in range and low frequency error using the m + n/k divider based on a multi-phase clock. The proposed DFLL can realize an extremely wide frequency lock-in range compared to the conventional DFLL using a multiphase clock. Also, the frequency detection error between input and output signals can be kept within one phase difference of the multi-phase clock. As a result, the steady-state frequency error of the output signal is also within one phase difference of the multi-phase clock. These characteristics were confirmed by simulation using Verilog-HDL, a hardware description language.

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《International journal of innovative computing, information and control》 |2022年第6期|1979-1988|共10页
作者
MITSUTOSHI YAHARA; KUNIAKI FUJIMOTO; DAISHI NISHIGUCHIYUJIRO HARADAMASAAKI FUKUHARA;
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Department of Medical Care and Welfare Engineering Tokai University 9-1-1, Toroku, Higashi-ku, Kumamoto-shi, Kumamoto 862-8652, Japan;

Department of Electronics and Intelligent Systems Engineering Tokai University 9-1-1, Toroku, Higashi-ku, Kumamoto-shi, Kumamoto 862-8652, Japan;

Graduate School of Information and Telecommunication Engineering Tokai University 2-3-23, Takanawa, Minato-ku, Tokyo 108-8619, JapanDepartment of Electrical and Electronic Engineering National Institute of Technology, Kurume College 1-1-1, Komorino, Kurume-shi, Fukuoka 830-8555, Japan;

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正文语种英语
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关键词
Frequency-locked loop; Multi-phase clock; Frequency error; Divider; PLL;

DIGITAL FREQUENCY-LOCKED LOOP WITH WIDE LOCK-IN RANGE AND LOW FREQUENCY ERROR BASED ON MULTI-PHASE CLOCK

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