Evolvable hardware-based fault-tolerant hardware design is an efficient approach to self-adaptability. It is an essential feature to mitigate errors on the fly. But there are two issues while designing an adder using the evolutionary hardware (EHW) approach: scalability issues in circuit representation and a low error recovery speed due to many evolutions. To avoid scalability issues, we designed an optimized virtual reconfiguration circuit (VRC) for adder. In this paper, we introduce the chromosome reconstruction algorithm for evolving the circuit to recover faults in an adder circuit at a faster speed. The proposed self-healing adder design is implemented on a single FPGA using an intrinsic approach. The complete hardware is designed on a Proasic A3PE3000 FPGA. Compared to existing work, the proposed work’s resource utilization is optimal.
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