Development of SiPMs (Silicon Photomultipliers) carried out in Semi-Conductor Laboratory (SCL) CMOS 8inch fabrication facility for photon-counting applications. A dedicated process engineering vehicle (FEV) was designed for the process development and optimisation. SiPM designs employing different inter-pixel isolations i.e. implant or oxide-trench isolations were evaluated. The n+/p-well diode with virtual guard ring architecture was adopted for the pixel. The PEV consisted of SiPM sensors of different pixel size (l0um & 50um), and square array sizes (1.5 & 3 mm) in addition to other process and device test structures used for process feedback and monitoring. A custom process sequence was designed in such a way that the avalanche photodiode and high-resistance poly modules exhibit the same electrical parameters (V_(bd) & R_(poly)) in the integrated process employing implant and trench isolation respectively, by maintaining the thermal budgets. Technology Computer-aided Design (TCAD) simulations were used to support the process development, particularly for the optimisation of implant process conditions used for p-well and pixel isolation. The full-flow is 12 mask process, and typically consists of about 100 process steps with 20 inline metrology & inspection steps for process control. 4um thick p-epi (on p+ substrate) wafers were used for the device development. The SiPMs were demonstrated to have required performance in terms of dark current and dark count rate. The developed SiPMs have low dark currents (5 nA/cm2) and breakdown voltage of about 22 V.
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