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机译:Characterization of Time Delay in Power Hardware in the Loop Setups
Univ Strathclyde, Inst Energy & Environm, Glasgow G1 1XQ, Lanark, Scotland;
Siemens Gamesa Renewable Energy, Glasgow ML4 3BF, Lanark, Scotland;
Univ Strathclyde, Elect Power Syst, Glasgow G1 1XQ, Lanark, ScotlandUniv Strathclyde, Power Network Demonstrat Ctr, Glasgow G1 1XQ, Lanark, Scotland;
Delays; Delay effects; Power system stability; Real-time systems; Hardware; Couplings; Stability analysis; Component testing; delay identification; power hardware in the loop (PHIL); real-time simulation; time delay;