A CT 2–2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction

Mitsuya Fukazawa; Takashi Oshima; Masaki FujiwaraKatsuki TateyamaAtsushi OchiRaed AlsubaieTetsuo Matsui

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A CT 2–2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction

机译：A CT 2–2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction

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This article presents a continuous-time (CT) multistage noise-shaping (MASH) delta–sigma (inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" tex-math notation="LaTeX"$Delta Sigma$ /tex-math/inline-formula) analog-to-digital converter (ADC) with enhanced tolerance to temperature and operating-frequency variations through on-chip multi-rate (MR) background calibration based on the least-mean-square (LMS) algorithm. The proposed digital calibration, which combines MR operation, post-conditioners, and pseudorandom-noise injection at the quantizer input, efficiently and accurately matches digital transfer functions to the corresponding analog ones for cancellation of quantization error. The first modulator in the proposed MASH ADC considers sufficient quantizer delay and reduces input-signal leakage into the second modulator to enable successful quantization-error transmission while minimizing distortion in the second stage, which cannot be tolerated in the case of calibrated digital noise-cancellation filter. A CT 2–2 MASH inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" tex-math notation="LaTeX"$Delta Sigma $ /tex-math/inline-formula ADC prototype fabricated in 40-nm CMOS achieves the dynamic range (DR) of 79 dB and the signal-to-noise and distortion ratio (SNDR) of 78.5 dB over an 8-MHz bandwidth with 7.3-mW analog power and 16-mW digital power, reaching Schreier figure of merit (FoMs) of 168.9 dB, and demonstrates conversion-accuracy robustness within 1-dB SNDR fluctuation for temperature variations from ?40° to 125° and within 2-dB SNDR degradation for frequency variations of 20 range.

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《IEEE Journal of Solid-State Circuits》 |2021年第10期|2943-2955|共13页
作者
Mitsuya Fukazawa; Takashi Oshima; Masaki FujiwaraKatsuki TateyamaAtsushi OchiRaed AlsubaieTetsuo Matsui;
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作者单位

Renesas Electronics Corporation, Kodaira, Japan;

Research and Development Group, Hitachi Ltd., Kokubunji, Japan;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
Calibration; Multi-stage noise shaping; Modulation; Transfer functions; Delays; Finite impulse response filters; Inspection;

A CT 2–2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction

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