...
机译:Performance and communication energy constrained embedded benchmark for fault tolerant core mapping onto NoC architectures
Department of Electronics and Communication Engineering, National Institute of Technology Warangal, India;
School of Electronics Systems and Automation, Digital University of Kerala (IIITM-Kerala), Trivendrum, India;
system-on-chip; SoC; network-on-chip; NoC; core; core mapping; core failure; fault tolerance; FT; multimedia benchmarks; communication energy; system performance; execution time;