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首页> 外文期刊>IEEE Transactions on Industrial Electronics >ZVS Design in Full-SiC Three-Level Neutral-Point-Clamped DC#x2013;DC Converter Considering Quasi-Linear Output Capacitance $C_{oss}$
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ZVS Design in Full-SiC Three-Level Neutral-Point-Clamped DC#x2013;DC Converter Considering Quasi-Linear Output Capacitance $C_{oss}$

机译：ZVS Design in Full-SiC Three-Level Neutral-Point-Clamped DC#x2013;DC Converter Considering Quasi-Linear Output Capacitance $C_{oss}$

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摘要

The three-level neutral-point-clamped (TLNPC) dc#x2013;dc converter is a popular topology for applications with high input voltage due to its simplicity of modulation, capability of withstanding high input voltage, and zero-voltage-switching (ZVS) operation. Regarding mitigating the voltage ringing on secondary side, energy recovery approach is preferred to RCD approach for the sake of high efficiency and small component counts. This article demonstrates that, using recovery approach in a Silicon Carbide (SiC)-based TLNPC dc#x2013;dc converter causes hard-switching of the outer switches due to the quasi-linear output capacitance $C_{oss}$ of SiC mosfet s. The ZVS design of a full-SiC TLNPC converter must not follow conventional methods for Silicon (Si)-based converters. To address this issue, a modified design approach, which can guarantee ZVS of all switches in a full-SiC TLNPC dc#x2013;dc converter, is introduced and discussed. All of the analysis is verified on a 3 kW full-SiC TLNPC prototype, which has rated input voltage of 1.2 kV, output voltage of 600 V, and achieves ZVS in the output power range of 1.2#x2013;3 kW.

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