This approach to introducing design in a computer architecture course allows the study of a wide variety of high-level architectural concepts such as pipelining, cache memories, and floating-point adders. The Verilog-based computational model provides a framework for students to describe, design, and test sophisticated digital systems at the appropriate abstraction level (RTL). The model uses a small subset of thc industry-standard Verilog HDL, which is easy to learn and builds on the students' experience with the C and C++ programming languages. Students use a 32-page Verilog Manual and a 12-page paper on this Verilog-based computational model and how to realize the model in digital circuits. Used with a free Verilog simulator, these Web-based materials give computer architecture instructors the ability to teach design. The materials are flexible and provide instructors with the freedom to modify the approach to integrate them with their current instructional needs. Over a dozen universities have requested permission to copy the materials and hand them out to their students.
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