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Inter-FPGA interconnect topologies exploration for multi-FPGA systems

机译：Inter-FPGA interconnect topologies exploration for multi-FPGA systems

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摘要

Prototyping using multi-FPGA systems offers significant advantages over simulation and emulation based pre-silicon verification techniques. Multi-FPGA prototyping follows a complex design flow where the quality of associated tools and the architecture of interconnect topology play a very important role in the performance of final prototyped design. A well designed interconnect topology may remain underutilized because of a poor routing tool and vice versa. This makes the selection of a good routing tool and the exploration of interconnect topologies extremely important for the quality of final design. In this work, we present a detailed comparison between six inter-FPGA interconnect topologies. We present a generic routing tool and for each topology, ten large, complex benchmarks are prototyped on four FPGA boards using this tool. Experimentation reveals that fully customized interconnect topology using a hybrid combination of direct two and multi point tracks gives the best frequency results for all the FPGA boards. On average, this topology gives 26.2, 28.5, 9.5, 32.1 and 12.4 better frequency results as compared to five other interconnect topologies. We also perform routing time comparison and the topology using generic hybrid combination of direct two and multi point tracks gives the best results. On average, this topology produces , , , , and better results as compared to five other topologies under consideration. Frequency-time tradeoff analysis along with flexibility and setup time of different topologies is also performed. It reveals that a partially customized topology with hybrid combination of direct two and multi point tracks gives the best frequency-time tradeoff for smaller FPGA boards while a partially customized topology with switch-based and multi point connections gives the best results for larger FPGA boards with reasonable flexibility and moderate setup time.

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