An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

Wei H.; Chan C.-H.; Chio U.-F.Sin S.-W.U S.-P.Martins R. P.Maloberti F.

首页> 外文期刊>IEEE Journal of Solid-State Circuits >An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

【24h】

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

机译：An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相关主题

摘要

An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low-power and small-area resistive DAC and associated highly integrated circuit implementation, the proposed SAR ADC achieves rapid conversion rate, low power, and compact area, leading to SNDR of 44.5 dB and SFDR of 54.0 dB, at 400 MS/s with 1.9-MHz input. The measured FOM is 73 fJ/conversion-step at 400 MS/s from 1.2-V supply and 42 fJ/conversion-step at 250 MS/s from a 1-V supply. The active area with the digital calibration is 0.028 ${hbox {mm}}^{2}$.

著录项

来源
《IEEE Journal of Solid-State Circuits》 |2012年第11期|2763-2772|共10页
作者
Wei H.; Chan C.-H.; Chio U.-F.Sin S.-W.U S.-P.Martins R. P.Maloberti F.;
展开▼
作者单位

The State Key Lab of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China;

展开▼
收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
2-b-per-cycle (2 b/C); Analog-to-digital converter (ADC); resistive DAC; successive approximation register (SAR);

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

摘要

著录项

相关主题

期刊订阅