A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing

Yang J.

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A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing

机译：A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing

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摘要

An asynchronous 6 bit 1 GS/s ADC is achieved by time interleaving two ADCs based on the binary successive approximation (SA) algorithm using a series capacitive ladder. The semi-closed loop asynchronous technique eliminates the high internal clocks and significantly speeds up the SA algorithm. A key feature to reduce the power in this design involves relaxing the comparator requirements using an error correction technique, which can be viewed as an extension of the SA algorithm to remove degradation due to metastability. Fabricated in 65 nm CMOS with an active area of ${hbox {0.11~mm}}^{2}$, it achieves a peak SNDR of 31.5 dB at 1$~$ GS/s sampling rate and has a total power consumption of 6.7 mW.

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来源
《IEEE Journal of Solid-State Circuits》 |2010年第8期|共10页
作者
Yang J.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类 NULL;
关键词
Analog-to-digital conversion; asynchronous logic circuits; binary successive approximation algorithm; cognitive radios; metastability; semi-closed loop; series capacitor array; time-interleaving;

A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing

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