A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

Liu C.-C.

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A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

机译：A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

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摘要

This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81 and 50, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13- $mu{hbox {m}}$ 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 $~$dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only $hbox{195}times hbox{265} mu{hbox {m}}^{2}$.

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来源
《IEEE Journal of Solid-State Circuits》 |2010年第4期|共10页
作者
Liu C.-C.;
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作者单位

Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
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关键词
Analog-to-digital converter; energy efficient; low power; successive approximation register;

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

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