Cluster based MPSoC architecture: an on-chip message passing implementation

Brillu Romain; Pillement Sebastien; Lemonnier FabriceMillet Philippe

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Cluster based MPSoC architecture: an on-chip message passing implementation

机译：Cluster based MPSoC architecture: an on-chip message passing implementation

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摘要

This paper proposes a hardware memory management unit to implement an on-chip message passing protocol for cluster based multi-processors system on chip architectures. Within the architecture each cluster is composed of general purpose processors or digital signal processors, along with a memory. To maintain the coherence of the memory a hardware memory management unit is added in the cluster to increase the performance and support an on-chip message passing communication. The hardware memory management unit has the capacity to allocate, control and limit the access to the memory. In order to show the benefit of our architecture a performance comparison over a classical flat architecture and against a state of the art architecture is driven. The results show an improvement that ranges from 1.2 to 21.77 over these two architectural models. Finally the hardware cost overhead is studied.

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来源
《Design automation for embedded systems》 |2013年第4期|587-607|共21页
作者
Brillu Romain; Pillement Sebastien; Lemonnier FabriceMillet Philippe;
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作者单位

Univ Nantes, LUNAM Univ, IETR, F-44306 Nantes, France;

Thales Res & Technol, F-91767 Palaiseau, France;

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原文格式 PDF
正文语种英语
中图分类一般性问题;
关键词
MPSoC; Cluster; Shared memory; Distributed memory; Hardware memory management unit;

Cluster based MPSoC architecture: an on-chip message passing implementation

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