Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

Gao X.

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Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

机译：Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

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摘要

This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 $,mu{hbox {m}}$ CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is $${-}$ 80 dBc. The PLL consumes 3.8$~$ mW while the in-band phase noise is $-hbox{121~dBc/Hz}$ at 200 $~$kHz and the output jitter integrated from 10 kHz to 100$~$ MHz is ${hbox {0.3~ps}}_{rm rms}$.

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来源
《IEEE Journal of Solid-State Circuits》 |2010年第9期|共13页
作者
Gao X.;
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authorLink("Gao, X.");

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类 NULL;
关键词
Clock generation; clock multiplier; clocks; frequency multiplication; frequency synthesizer; low jitter; low phase noise; low power; low spur; phase detector; phase-locked loop (PLL); sampling phase detector; sub-sampling phase detector;

Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

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