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外文期刊>IEEE Journal of Solid-State Circuits
>Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM
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Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM
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机译：Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM
This paper proposes schemes for the direct measurement of bit-line (BL) voltage swing, sense amplifier (SA) offset voltage, and word-line (WL) pulse width, demonstrated in a 40 nm CMOS 32 kb fully functional SRAM macro with <;2 area penalty. This is the first such scheme to enable the optimal tuning of WL-pulse (WLP) width according to on-site measurement results for BL voltage swing, dynamic read stability, and write margin, all of which depend on WLP width. It also eliminates the need for additional margins related to BL voltage swing, which has conventionally been required to ensure adequate tolerances against simulation errors and inaccurate estimation of SA offset voltage. This opens up possibilities for a more aggressive approach to deal with WLP width instead of only ensuring the target BL voltage swing.
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