A 6-formula formulatype='inline' img src='/images/tex/241.gif' alt='mu'  /formulaW Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

Guo J.

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A 6-formula formulatype='inline' img src='/images/tex/241.gif' alt='mu' /formulaW Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

机译：A 6-formula formulatype="inline" img src="/images/tex/241.gif" alt="mu" /formulaW Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

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An output-capacitorless low-dropout regulator (LDO) compensated by a single Miller capacitor is implemented in a commercial 90-nm CMOS technology. The proposed LDO makes use of the small transistors realized in nano-scale technology to achieve high stability, fast transient performance and small voltage spikes under rapid load-current changes without the need of an off-chip capacitor connected at the LDO output. Experimental result verifies that the proposed LDO is stable for a capacitive load from 0 to 50 pF (estimated equivalent parasitic capacitance from load circuits) and with load capability of 100 mA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the embedded power transistor promptly. The measured power consumption is only 6 $mu$W under a 0.75-V supply. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 $mu$s.

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《IEEE Journal of Solid-State Circuits》 |2010年第9期|共10页
作者
Guo J.;
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authorLink("Guo, J.");

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类 NULL;
关键词
Capacitor-less; low-dropout regulator (LDO); nano-scale technology; transient response;

A 6-formula formulatype='inline' img src='/images/tex/241.gif' alt='mu' /formulaW Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

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