A survey on partitioning models, solution algorithms and algorithm parallelization for hardware/software co-design

Hou Neng; Yan Xiaohu; He Fazhi

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A survey on partitioning models, solution algorithms and algorithm parallelization for hardware/software co-design

机译：A survey on partitioning models, solution algorithms and algorithm parallelization for hardware/software co-design

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In electronic design automation, hardware/software co-design significantly reduces the time-to-market and improves the performance of embedded systems. With the increasing scale of applications and complexity of hardware architecture of embedded systems, hardware/software co-design is still a research hotspot. As hardware/software co-design is a wide topic, this paper focuses on major developments of three important aspects related to hardware/software partitioning, which has great effects on the performance of embedded systems. Firstly, various partitioning models including hardware architectures and abstract models are surveyed. Secondly, classical and new algorithms for hardware/software partitioning are classified and analyzed. Thirdly, existing parallel algorithms for hardware/software co-design are discussed in details. Finally, possible research directions are pointed out in conclusion.

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《Design automation for embedded systems》 |2019年第2期|57-77|共21页
作者
Hou Neng; Yan Xiaohu; He Fazhi;
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作者单位

Wuhan Univ, Sch Comp Sci, Wuhan 430072, Hubei, Peoples R China;

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原文格式 PDF
正文语种英语
中图分类一般性问题;
关键词
Hardware; software co-design; software partitioning; Partition model; Solution algorithm; Algorithm parallelization;

A survey on partitioning models, solution algorithms and algorithm parallelization for hardware/software co-design

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