11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications

Kocaman N.; Garg A.; Raghavan B.Delong CuiVasani A.Tang K.Deyi PiHaitao TongFallahi S.Wei ZhangSingh U.Jun CaoBo ZhangMomtaz A.

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11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications

机译：11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications

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摘要

In this paper, an 11.3 Gbps CMOS SONET compliant transceiver designed to work in both RZ and NRZ data formats is presented. Using a configurable high-speed transmit path utilizing an AND gate and a duty cycle adjustment circuit, the transmitter can switch output format between RZ and NRZ. The TX driver exhibits 17 ps rise/fall times, 0.25 psrms RJ, and 2 pspp DJ. In RZ mode, TX output duty cycle can be adjusted within 40-60 range. To improve input sensitivity in both RZ and NRZ reception, the receiver incorporates a limiting amplifier with a distributed threshold adjustment circuit. It achieves 5 mVpp-diff RX input sensitivity with 0.54 UI high-frequency jitter tolerance. An adaptation scheme based on nested linear search is implemented to control the distributed threshold adjustment circuit. While demonstrating the integration of RZ/NRZ functionality into a single-chip solution using 65 nm CMOS technology, the transceiver core occupies 1.36 mm2 and consumes 214 mW.

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来源
《IEEE Journal of Solid-State Circuits》 |2011年第12期|3089-3100|共12页
作者
Kocaman N.; Garg A.; Raghavan B.Delong CuiVasani A.Tang K.Deyi PiHaitao TongFallahi S.Wei ZhangSingh U.Jun CaoBo ZhangMomtaz A.;
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作者单位

Broadcom Corp., Irvine, CA, USA;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
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关键词
CMOS integrated circuits; NRZ to RZ conversion; SONET OC-192; duty cycle adjustment; optical communication; return-to-zero (RZ); threshold adjustment;

11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications

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