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机译:Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction
University of Michigan,;
Clocks; Delay; Error correction; Latches; Pipeline processing; Random access memory; Adaptive circuits; dynamic voltage and frequency scaling (DVFS); error correction; time borrowing; timing speculation; two-phase latches; variation tolerance;