A 4 GHz Continuous-Time ADC With 70 dB DR and 74 dBFS THD in 125 MHz BW

Bolatkale M.; Breems L.J.; Rutten R.Makinwa K.A.A.

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A 4 GHz Continuous-Time ADC With 70 dB DR and 74 dBFS THD in 125 MHz BW

机译：A 4 GHz Continuous-Time ADC With 70 dB DR and 74 dBFS THD in 125 MHz BW

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摘要

A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm2 including the modulator, clock circuitry and decimation filter.

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来源
《IEEE Journal of Solid-State Circuits》 |2011年第12期|2857-2868|共12页
作者
Bolatkale M.; Breems L.J.; Rutten R.Makinwa K.A.A.;
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作者单位

NXP Semicond., Eindhoven, Netherlands;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
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关键词
Analog-to-digital conversion; CMOS analog integrated circuits; base stations; continuous-time filters; continuous-time sigma-delta modulation; delta-sigma modulator; multi-bit; oversampling ADCs; radio receivers; wireless communication;

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A 4 GHz Continuous-Time ADC With 70 dB DR and 74 dBFS THD in 125 MHz BW

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