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机译:A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance
Dept. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA;
Digital CDR; clock phase calibration; data duty cycle error; linear delay cell; optimal sampling; power spectral density of random NRZ data; reference-less frequency acquisition;