Implantation of boron at sub-keV energies, combined with rapid thermal annealing in the temperature range from 900 to 1050 degrees C with soak times of 20 s or less results in activated junctions with depths of the order of 50 nm. These depths are consistent with roadmap estimates of transistor requirements for 100 nm scale devices for 16 Gb DRAM technology. (C) 1998 Elsevier Science S.A. All rights reserved. References: 7
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