The origin and nature of anomalous leakage currents in CMOS (complementary metalhyphen;oxidehyphen;semiconductor) integrated circuits are investigated. Studies of the voltage dependence of the leakage on both devices andp/njunctions show that device leakage originates from individual junctions, and is very similar to that found from electrically active stacking faults (EASFrsquo;s) studied by other workers.1In particular, a powerhyphen;law dependence (IRprop;VnR) is observed with exponents ranging fromn=3ndash;7.5. The onset of the anomalous leakage occurs at reversehyphen;bias voltages ranging from 2ndash;8 V. Etching studies of junctions with and without the anomalous leakage indicate a high correlation between the presence of the leakage and the occurrence of stacking faults intersecting thep/njunction boundary at the silicon surface. This correlation is confirmed by scanning electron microscope studies in the electronhyphen;beamhyphen;inducedhyphen;current (EBIC) mode. Every junction showing the anomalous leakage exhibits one or more EBIC sites along the perimeter defined by the intersection of thep/njunction boundary and the silicon surface. A detailed investigation of these sites using transmission electron microscopy reveals that in every case they are associated with a decorated stacking fault crossing the junction at this point. In no case has an undecorated stacking fault been identified as a leakage site. Implications of this result for reducing the anomalous leakage by gettering are discussed.
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